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MEMORY - EBI SDRAM Controller

EBI (External Bus Interface) SDRAM Controller allows to connect a SDRAM to the microcontroller.

Macros

#define SDRAM   ((void *)AVR32_EBI_CS1_ADDRESS)
 Pointer to SDRAM. More...
 
#define SDRAM_BANK_BITS   2
 The number of bank bits for this SDRAM (1 or 2). More...
 
#define SDRAM_CAS   2
 The minimal column address select (READ) latency for this SDRAM (1 to 3 SDRAM cycles). More...
 
#define SDRAM_COL_BITS   9
 The number of column bits for this SDRAM (8 to 11). More...
 
#define SDRAM_INIT_AUTO_REFRESH_COUNT   2
 The minimal number of AUTO REFRESH commands required during initialization for this SDRAM. More...
 
#define SDRAM_ROW_BITS   13
 The number of row bits for this SDRAM (11 to 13). More...
 
#define SDRAM_SIZE
 SDRAM size. More...
 
#define SDRAM_STABLE_CLOCK_INIT_DELAY   100
 The minimal stable-clock initialization delay for this SDRAM. More...
 
#define SDRAM_TMRD   2
 The minimal mode register delay time for this SDRAM. More...
 
#define SDRAM_TR   7812
 The maximal refresh time for this SDRAM (0 to 4095 SDRAM cycles). More...
 
#define SDRAM_TRAS   37
 The minimal row address select time for this SDRAM (0 to 15 SDRAM cycles). More...
 
#define SDRAM_TRC   60
 The minimal row cycle time for this SDRAM (0 to 15 SDRAM cycles). More...
 
#define SDRAM_TRCD   15
 The minimal row to column delay time for this SDRAM (0 to 15 SDRAM cycles). More...
 
#define SDRAM_TRFC   66
 The minimal refresh cycle time for this SDRAM. More...
 
#define SDRAM_TRP   15
 The minimal row precharge time for this SDRAM (0 to 15 SDRAM cycles). More...
 
#define SDRAM_TWR   14
 The minimal write recovery time for this SDRAM (0 to 15 SDRAM cycles). More...
 
#define SDRAM_TXSR   67
 The minimal exit self refresh time for this SDRAM (0 to 15 SDRAM cycles). More...
 

Functions

void sdram_enter_self_refresh (void)
 Set the SDRAM in self refresh mode. The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. More...
 
void sdram_exit_self_refresh (void)
 Exit from the SDRAM self refresh mode, inhibits self refresh mode. More...
 
void sdramc_init (unsigned long hsb_hz)
 Initializes the AVR32 SDRAM Controller and the connected SDRAM(s). More...
 

#define SDRAM   ((void *)AVR32_EBI_CS1_ADDRESS)

Pointer to SDRAM.

Referenced by main(), and sdramc_init().

#define SDRAM_BANK_BITS   2

The number of bank bits for this SDRAM (1 or 2).

Referenced by sdramc_init().

#define SDRAM_CAS   2

The minimal column address select (READ) latency for this SDRAM (1 to 3 SDRAM cycles).

Unit: tCK (SDRAM cycle period).

Referenced by sdramc_init().

#define SDRAM_COL_BITS   9

The number of column bits for this SDRAM (8 to 11).

Referenced by sdramc_init().

#define SDRAM_INIT_AUTO_REFRESH_COUNT   2

The minimal number of AUTO REFRESH commands required during initialization for this SDRAM.

Referenced by sdramc_init().

#define SDRAM_ROW_BITS   13

The number of row bits for this SDRAM (11 to 13).

Referenced by sdramc_init().

#define SDRAM_SIZE
Value:
(SDRAM_DBW >> 4)))
#define SDRAM_COL_BITS
The number of column bits for this SDRAM (8 to 11).
Definition: sdramc.h:71
#define SDRAM_BANK_BITS
The number of bank bits for this SDRAM (1 or 2).
Definition: sdramc.h:65
#define SDRAM_ROW_BITS
The number of row bits for this SDRAM (11 to 13).
Definition: sdramc.h:68

SDRAM size.

Referenced by main().

#define SDRAM_STABLE_CLOCK_INIT_DELAY   100

The minimal stable-clock initialization delay for this SDRAM.

Unit: us.

Referenced by sdramc_init().

#define SDRAM_TMRD   2

The minimal mode register delay time for this SDRAM.

LOAD MODE REGISTER command to ACTIVE or REFRESH command delay. Unit: tCK (SDRAM cycle period).

Referenced by sdramc_init().

#define SDRAM_TR   7812

The maximal refresh time for this SDRAM (0 to 4095 SDRAM cycles).

Refresh period. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRAS   37

The minimal row address select time for this SDRAM (0 to 15 SDRAM cycles).

ACTIVE-to-PRECHARGE command delay. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRC   60

The minimal row cycle time for this SDRAM (0 to 15 SDRAM cycles).

ACTIVE-to-ACTIVE command delay. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRCD   15

The minimal row to column delay time for this SDRAM (0 to 15 SDRAM cycles).

ACTIVE-to-READ/WRITE command delay. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRFC   66

The minimal refresh cycle time for this SDRAM.

AUTO REFRESH command period. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TRP   15

The minimal row precharge time for this SDRAM (0 to 15 SDRAM cycles).

PRECHARGE command period. Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TWR   14

The minimal write recovery time for this SDRAM (0 to 15 SDRAM cycles).

Unit: ns.

Referenced by sdramc_init().

#define SDRAM_TXSR   67

The minimal exit self refresh time for this SDRAM (0 to 15 SDRAM cycles).

Exit SELF REFRESH to ACTIVE command delay. Unit: ns.

Referenced by sdramc_init().

void sdram_enter_self_refresh ( void  )

Set the SDRAM in self refresh mode. The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking.

Note
Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.
An example of entering/exiting CPU sleep mode while keeping SDRAM content is : sdram_enter_self_refresh(); SLEEP(AVR32_PM_SMODE_STATIC); sdram_exit_self_refresh();
void sdram_exit_self_refresh ( void  )

Exit from the SDRAM self refresh mode, inhibits self refresh mode.

void sdramc_init ( unsigned long  hsb_hz)

Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).

Parameters
hsb_hzHSB frequency in Hz (the HSB frequency is applied to the SDRAMC and to the SDRAM).
Note
HMATRIX and SDRAMC registers are always read with a dummy load operation after having been written to, in order to force write-back before executing the following accesses, which depend on the values set in these registers.
Each access to the SDRAM address space validates the mode of the SDRAMC and generates an operation corresponding to this mode.

References ATPASTE2, i, SDRAM, SDRAM_BANK_BITS, SDRAM_CAS, SDRAM_COL_BITS, SDRAM_INIT_AUTO_REFRESH_COUNT, SDRAM_ROW_BITS, SDRAM_STABLE_CLOCK_INIT_DELAY, SDRAM_TMRD, SDRAM_TR, SDRAM_TRAS, SDRAM_TRC, SDRAM_TRCD, SDRAM_TRFC, SDRAM_TRP, SDRAM_TWR, SDRAM_TXSR, sdramc_enable_muxed_pins(), sdramc_ns_delay, and sdramc_us_delay.

Referenced by board_init(), and main().