Atmel Software Framework

PLL Management

This group contains functions and definitions related to configuring and enabling/disabling on-chip PLLs.

A PLL will take an input signal (the source), optionally divide the frequency by a configurable divider, and then multiply the frequency by a configurable multiplier.

Some devices don't support input dividers; specifying any other divisor than 1 on these devices will result in an assertion failure. Other devices may have various restrictions to the frequency range of the input and output signals.

Example: Setting up PLL0 with default parameters

The following example shows how to configure and enable PLL0 using the default parameters specified using the configuration symbols listed above.

To configure, enable PLL0 using the default parameters and to disable a specific feature like Wide Bandwidth Mode (a UC3A3-specific PLL option.), you can use this initialization process.

struct pll_config pllcfg;
if (pll_is_locked(pll_id)) {
return; // Pll already running
}
pll_config_defaults(&pllcfg, 0);
pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
pll_enable(&pllcfg, 0);

When the last function call returns, PLL0 is ready to be used as the main system clock source.

Configuration Symbols

Each PLL has a set of default parameters determined by the following configuration symbols in the application's configuration file:

These configuration symbols determine the result of calling pll_config_defaults() and pll_get_default_rate().

Data Structures

struct  pll_config
 Hardware-specific representation of PLL configuration. More...
 

Macros

#define PLL_COUNT   0x3fU
 
#define PLL_INPUT_HZ   32768
 
#define PLL_OUTPUT_MAX_HZ   48000000
 
#define PLL_OUTPUT_MAX_HZ   96000000
 
#define PLL_OUTPUT_MAX_HZ   120000000
 
#define PLL_OUTPUT_MIN_HZ   24000000
 
#define PLLA_ID   0
 
#define PLLB_ID   1
 

Enumerations

enum  pll_source {
  PLL_SRC_SLCK_RC = OSC_SLCK_32K_RC,
  PLL_SRC_SLCK_XTAL = OSC_SLCK_32K_XTAL,
  PLL_NR_SOURCES
}
 PLL clock source. More...
 

Functions

static void pll_config_init (struct pll_config *p_cfg, enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
 
static void pll_config_read (struct pll_config *p_cfg, uint32_t ul_pll_id)
 
static void pll_config_write (const struct pll_config *p_cfg, uint32_t ul_pll_id)
 
static void pll_disable (uint32_t ul_pll_id)
 
static void pll_enable (const struct pll_config *p_cfg, uint32_t ul_pll_id)
 
static uint32_t pll_is_locked (uint32_t ul_pll_id)
 

Chip-specific PLL characteristics

#define NR_PLLS   2
 Number of on-chip PLLs. More...
 

PLL configuration

#define pll_config_defaults(cfg, pll_id)
 Initialize PLL configuration using default parameters. More...
 
#define pll_get_default_rate(pll_id)
 Get the default rate in Hz of pll_id. More...
 

Interaction with the PLL hardware

static int pll_wait_for_lock (unsigned int pll_id)
 Wait for PLL pll_id to become locked. More...
 
static void pll_enable_source (enum pll_source e_src)
 Enable the source of the pll. More...
 
static void pll_enable_config_defaults (unsigned int ul_pll_id)
 Enable the pll with the default configuration. More...
 

#define NR_PLLS   2
#define pll_config_defaults (   cfg,
  pll_id 
)
Value:
CONFIG_PLL##pll_id##_SOURCE, \
CONFIG_PLL##pll_id##_DIV, \
CONFIG_PLL##pll_id##_MUL)
static void pll_config_init(struct pll_config *p_cfg, enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
Definition: samg/pll.h:103

Initialize PLL configuration using default parameters.

After this function returns, cfg will contain a configuration which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) times the frequency of CONFIG_PLLx_SOURCE.

Parameters
cfgThe PLL configuration to be initialized.
pll_idUse defaults for this PLL.

Referenced by sysclk_init(), and sysclk_set_source().

#define PLL_COUNT   0x3fU

Referenced by pll_config_init().

#define pll_get_default_rate (   pll_id)
Value:
((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \
* CONFIG_PLL##pll_id##_MUL) \
/ CONFIG_PLL##pll_id##_DIV)
static uint32_t osc_get_rate(uint32_t ul_id)
Definition: samg/osc.h:177

Get the default rate in Hz of pll_id.

Referenced by sysclk_get_main_hz().

#define PLL_INPUT_HZ   32768
#define PLL_OUTPUT_MAX_HZ   48000000

Referenced by pll_config_init().

#define PLL_OUTPUT_MAX_HZ   96000000
#define PLL_OUTPUT_MAX_HZ   120000000
#define PLL_OUTPUT_MIN_HZ   24000000

Referenced by pll_config_init().

#define PLLA_ID   0
#define PLLB_ID   1

Referenced by pll_is_locked().

enum pll_source

PLL clock source.

Enumerator
PLL_SRC_SLCK_RC 

Internal 32KHz RC oscillator.

PLL_SRC_SLCK_XTAL 

External 32kHz crystal oscillator.

PLL_NR_SOURCES 

Number of PLL sources.

static void pll_config_init ( struct pll_config p_cfg,
enum pll_source  e_src,
uint32_t  ul_div,
uint32_t  ul_mul 
)
inlinestatic
Note
The SAMG PLL hardware interprets mul as mul+1. For readability the hardware mul+1 is hidden in this implementation. Use mul as mul effective value.

References Assert, pll_config::ctrl, osc_get_rate(), PLL_COUNT, PLL_NR_SOURCES, PLL_OUTPUT_MAX_HZ, and PLL_OUTPUT_MIN_HZ.

Referenced by pll_enable_config_defaults().

static void pll_config_read ( struct pll_config p_cfg,
uint32_t  ul_pll_id 
)
inlinestatic

References Assert, pll_config::ctrl, NR_PLLS, and PLLA_ID.

static void pll_config_write ( const struct pll_config p_cfg,
uint32_t  ul_pll_id 
)
inlinestatic
static void pll_disable ( uint32_t  ul_pll_id)
inlinestatic
Note
This will only disable the selected PLL, not the underlying oscillator (mainck).

References Assert, NR_PLLS, PLLA_ID, pmc_disable_pllack(), and pmc_disable_pllbck().

static void pll_enable ( const struct pll_config p_cfg,
uint32_t  ul_pll_id 
)
inlinestatic
void pll_enable_config_defaults ( unsigned int  pll_id)
inlinestatic

Enable the pll with the default configuration.

PLL is enabled, if the PLL is not already locked.

Parameters
pll_idThe ID of the PLL to enable.

References Assert, CONFIG_PLL0_DIV, CONFIG_PLL0_MUL, CONFIG_PLL0_SOURCE, pll_config_init(), pll_enable(), pll_enable_source(), and pll_is_locked().

Referenced by genclk_enable_source().

void pll_enable_source ( enum pll_source  src)
inlinestatic

Enable the source of the pll.

The source is enabled, if the source is not already running.

Parameters
srcThe ID of the PLL source to enable.

References Assert, osc_enable(), osc_wait_ready(), PLL_SRC_SLCK_RC, and PLL_SRC_SLCK_XTAL.

Referenced by pll_enable_config_defaults(), sysclk_init(), and sysclk_set_source().

static uint32_t pll_is_locked ( uint32_t  ul_pll_id)
inlinestatic
static int pll_wait_for_lock ( unsigned int  pll_id)
inlinestatic

Wait for PLL pll_id to become locked.

Todo:
Use a timeout to avoid waiting forever and hanging the system
Parameters
pll_idThe ID of the PLL to wait for.
Return values
STATUS_OKThe PLL is now locked.
ERR_TIMEOUTTimed out waiting for PLL to become locked.

References Assert, NR_PLLS, and pll_is_locked().

Referenced by sysclk_init(), and sysclk_set_source().