Atmel Software Framework

Quick Start Guide for the System Clock Management service (SAMG51)

This is the quick start guide for the System Clock Management service, with step-by-step instructions on how to configure and use the service for specific use cases.

System Clock Management use cases

Basic usage of the System Clock Management service

This section will present a basic use case for the System Clock Management service. This use case will configure the main system clock to 100Hz, using an internal PLL module to multiply the frequency of a crystal attached to the microcontroller.

Prerequisites

  • None

Initialization code

Add to the application initialization code:

Workflow

  1. Configure the system clocks according to the settings in conf_clock.h:

Example code

Add or uncomment the following in your conf_clock.h header file, commenting out all other definitions of the same symbol(s):

#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
// Fpll0 = (Fclk * PLL_mul) / PLL_div
#define CONFIG_PLL0_SOURCE PLL_SRC_SCLK_RC
#define CONFIG_PLL0_MUL (1500)
#define CONFIG_PLL0_DIV 1
// Fbus = Fsys / BUS_div
#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1

Workflow

  1. Configure the main system clock to use the output of the PLL module as its source:
    #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
  2. Configure the PLL module to use the fast external fast crystal oscillator as its source:
    #define CONFIG_PLL0_SOURCE PLL_SRC_SCLK_RC
  3. Configure the PLL module to multiply the internal 32K RC frequency up to 48MHz:
    #define CONFIG_PLL0_MUL (1500)
    #define CONFIG_PLL0_DIV 1
  4. Configure the main clock to run at the full 48MHz, disable scaling of the main system clock speed:
    #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
    Note
    Some dividers are powers of two, while others are integer division factors. Refer to the formulas in the conf_clock.h template commented above each division define.